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    Home » Huawei redesigns chips to work around manufacturing limits
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    Huawei redesigns chips to work around manufacturing limits

    Dawn SolanoBy Dawn SolanoMay 27, 20262 Mins Read
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    Chinese tech giant HUAWEI is proposing a new approach to semiconductor development that could help it compete in advanced chipmaking despite ongoing US trade restrictions.

    In a recent announcement, HUAWEI introduced what it calls the “Tau (τ) Scaling Law” and a chip architecture design known as “LogicFolding,” which the company said could improve chip performance without relying solely on shrinking transistor sizes.

    For decades, the semiconductor industry followed Moore’s Law; the idea that chip performance improves as manufacturers pack more, smaller transistors into processors. However, as chips approach physical and engineering limits, further shrinking them has become increasingly expensive and difficult.

    HUAWEI said its proposed Tau Scaling Law puts the focus from transistor size to signal delay, or the amount of time it takes electronic signals to travel inside a chip.

    By reorganizing chip layouts and shortening signal paths, the company said chips can operate faster and more efficiently even when built using older manufacturing processes.

    The company described LogicFolding as a method that restructures circuits to reduce internal communication delays, improve energy efficiency and increase what HUAWEI called “effective transistor density.”

    Since 2019, the company has faced US sanctions that limited its access to advanced chipmaking technologies, including cutting-edge manufacturing tools and partnerships tied to companies such as TSMC and ASML.

    Those restrictions have made it difficult for HUAWEI to manufacture chips using the world’s most advanced process nodes, such as 2-nanometer technology currently being pursued by leading chipmakers.

    HUAWEI now appears to be banking on architectural innovation, which can compensate for manufacturing disadvantages.

    According to the company, future chips using LogicFolding could eventually achieve density and performance levels comparable to “1.4nm-class” chips by 2031, despite using less advanced fabrication processes.

    The company said it has already mass-produced hundreds of chips using related technologies over the past six years and plans to introduce the first Kirin smartphone chip using LogicFolding later in 2026.

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    Dawn Solano

    Technology editor for The Philippine STAR

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